Advancements in science and technology have triggered the innovation of microelectronic technology in the recent years. This technology bears the tremendous potential to permanently revolutionize industrial and consumer products and innovative applications that were unthinkable just a few years ago. In the present day, we are surrounded by various electronic devices that transfer data from one device to another through the internet, thus creating Internet of Things (often known as IoT). Though tech companies and analysts forecast a huge growth in the IoT and the data generated by the same, relying on these technologies to store such an enormous amount of data has certainly been the biggest challenge.
The use and potential misuse of large volumes of data are a matter of concern for the end users and the vendors alike. Let’s take a look at the challenges and the best possible solutions to the same:
- Adopting right approaches: A part of a robust business continuity plan is to have a backup plan in place if the data gets corrupted or accidentally deleted. Avoiding data corruption or restoring the correct data is possible only through the adoption of proper methods in memory elements and arrays. Latches and flip-flops make an ideal choice for preserving the correctness of the data stored in memory elements. ECCs accommodates simple single error correcting (SEC) or double error detecting (DED) codes to correct more than a single error. These codes are important for scaled-down technologies and high-density memory arrays.
- However, adoption of these powerful ECCs brings along high area overhead and a significant impact on performance. This is mainly due to the storage of a greater number of check bits and more complex encoding and decoding structures.
- Memory Interleaving: There are advanced ECCs to cope up with multiple upsets. One of the most common approaches to deal with multiple errors is to use interleaving in the physical arrangement of memory cells. This helps in segregating the cells that belong to the same logical word. This can be adopted together with SEC/DED codes to protect memory arrays against MBUs. Interleaving cannot be used for register files or small memories because its use may have an impact on floor planning access time and power consumption. Though interleaving generally requires complex and expensive decoding circuitry, it cannot guarantee error correction when the same memory word is affected by two errors.
Let’s take a look at the write-ups that provide a comprehensive reference for the theoretical and practical aspects of innovative approaches for reliable data storage.
- Accurate Model for Application Failure Due to Transient Faults in Caches: This research conducted by Mehrtash Manoochehri and Michel Duboise proposes a solution for the evaluation of cache reliability, in the presence of multi-bit faults, expressed in terms of the failure in time (FIT) metric. In this research paper, authors introduce the concept PARMA+ model which enables FIT rate estimates under all possible sequences.
- High Performance Robust Latches: This research paper, co-authored by Martin Omana and Daniele Rossi, recommends a high-performance robust latch called HiPeR latch. This is insensitive to TFs affecting its internal and output nods regardless of the energy of the radiation particle. The research article also discusses the modified version of the latch and its benefits.
- Concerting: Squeezing in Cache Content to Operate at Near Threshold Voltage: In this research article, Alexandra Ferreron and her colleagues have proposed that large SRAM structures, such as the last-level cache (LLC), enable operation at low voltages with conventional SRAM cells.
In conclusion, it can be summarized that electronic objects can certainly exchange a huge amount of data as the data-exchange is enabled by the IoT. However, storing it in a reliable way will be challenging. Emphasizing the major challenges in reliable data storage and stimulating further research in the field are the needs of the hour.